In many power conversion applications, a plurality of power transistors are used to control the flow of power. These power transistors may be controlled by pulse width modulation (PWM) signals from PWM generators. The PWM signals may be isolated with pulse transformers, opto-couplers, digital isolators, etc., and then amplified with “gate drivers” for driving the power transistors. A problem exists in that different isolators, gate drivers and/or power transistors have different time delays in the PWM signal paths. These non-uniform PWM signal path delays cause the power transistors to turn on or off with non-ideal timing. Early turn-on or late turn-off may cause current shoot-through, and late turn-on may cause voltage spikes. In addition, PWM power conversion circuits are providing for faster power transistor switching to shrink size and cost of the power conversion applications, but PWM signal delays in the transistor gate drive circuitry remain constant, and thereby are becoming a larger portion of the PWM cycle. This results in increased power transistor stress that lowers reliability, and poor timing control that lowers power conversion efficiencies.